Particular but non-limitative applications of the embodiments are high bandwidth consuming applications, such as multimedia applications, for example, implemented in set-top boxes.
Consumer expectations are placing ever greater demands on the multimedia requirements of today's consumer electronic devices. Advanced graphical user interfaces drive the demand for Graphics Processor Unit (GPU) HD video demand for video acceleration. Full 1080p graphics and video (2D and 3D TV) is becoming a requirement on almost every consumer electronic device today. 4KP30 and 4KP60 video resolutions are also now available.
Such applications are implemented on System on Chips (SoCs) coupled to memories such as double data rate (DDR) memories, for example, or double rate synchronous dynamic random access memories (DDR SDRAM).
Those applications, which are quite high bandwidth consuming, lead to increases in the number of memory interfaces of System on Chips used in consumer markets.
It is, however, possible to offer a unified memory system even if multiple memory interfaces are physically presented in a System on Chip. This is achieved by interleaving traffic to handle the multiple memories interfaces. This is known by one skilled in the art as “address interleaving”.
Address interleaving aims also at achieving load balancing among the different memory interfaces.
Further, in order to be compliant with the latest generation of security requirements, it may be desirable to encrypt sensitive data stored in external memories, such as secured code and compressed video, for example.